What you will learn:
- Which emerging technologies are poised to potentially take over the memory space?
- Current state of NOR flash and SRAM.
- The top factor in cost and its impact on technology success.
The memory business is at an odd turning point. DRAM process migration seems to have slowed down and 3D is being talked about… NAND flash has gone through a relatively painful 3D transition and is now performing very well as 3D memory… and CMOS logic has reached Unsupported process geometry – chip memory.
“What?” You said the last point. What does this have to do with discrete memory chips, who says CMOS logic can’t support memory? Well, that’s an important point, so let’s take a look.
NOR Flash stops at 28:00
Like many other SoCs, most MCUs contain NOR flash for their code storage. NOR is cheap and can be used in almost all foundry CMOS logic processes. It has been so for decades. But no one has developed a way to fabricate inexpensive NOR flash on FinFET processes, so NOR is not available at process geometries smaller than 28 nm.This appears as a red line at figure 1which represents the relative cost of shrinking embedded NOR across processes.
If MCUs don’t migrate beyond 28 nm, and as long as other NOR-using SoCs don’t scale beyond 28 nm, this plateau might not be a problem. History tells us that’s unlikely.
Some MCU designs that have been implemented at 28 nm use an external serial NOR chip to carry code that is downloaded on demand into an SRAM cache on the MCU. While this can get expensive, it solves the current problem since SRAM uses six transistors per bit and NOR uses only one, and serial NOR chips are very cheap.
But this is only a temporary solution, as SRAM also faces challenges.
SRAM is not far behind
As the process shrinks, it becomes more and more challenging to shrink the SRAM along with the process. The IEEE International Solid-State Circuits Conference (ISSCC) tracks SRAM bit sizes in a historical chart that is updated annually.
The data in this chart from 90nm to 5nm shows that the area of the SRAM cells in the study chips has shrunk by an average of 17% per process node, while the process has shrunk by an average of 21%.Around 20 nm, in some processes, SRAM size and cost stop shrinking entirely (blue line in Figure 1)Either way, shrinking the SRAM is not as economical as logically justified, and over time the SRAM becomes more and more expensive (as part of the overall chip cost).
The industry seems to need a new memory technology that will allow designers to shrink their MCUs and SoCs as the process advances without worrying about redesigning their memory systems or enduring suboptimal cost improvements.
Is there something I can use to solve this puzzle?
Rescue of Emerging Memory
In fact, there is, and it’s in the form of emerging memories that are not mainstream today, but allow the industry to continue reducing chip costs through process scaling (black line in Figure 1). These emerging memories are the subject of a new report from Objective Analysis and Coughlin Associates: Emerging memories enter the next phase. This article is based on a small portion of the information contained in the 231-page report.
Today’s leading emerging memory technologies are PCM, MRAM, FRAM and ReRAM. Each has been in production and has been shipping for over five years. Several others are in development, hoping to make their mark on the industry.
As stand-alone memory chips, these were marketed to niche markets as standalones and didn’t make much headway due to cost. A paradox has kept them from making significant progress: they have to be cheaper than mainstream memories (DRAM, SRAM, NOR and NAND flash, and EEPROM) to gain mass acceptance, but until their shipments are comparable to existing technologies, they will still be cheaper than existing technologies. These mature technologies are more expensive. Over the years, this has hindered their growth and relegated them to market niches.
However, in embedded applications such as MCUs and SoCs, there are brick walls preventing the use of NOR flash, and these technologies are gaining acceptance. Their wafer volumes are also likely to increase dramatically in the near future.
Armed with this understanding, we were able to compile a 10-year forecast for memory revenue, forecasting annual revenue for both embedded and standalone emerging memory, as shown in Figure 1. figure 2, taken from the report. We had to use semi-log graphs to make the early years simply appear because they are so small today.
The chart shows emerging memory as MRAM, but in reality, it’s too early to tell which technology will actually win the race. What we do know is that only one of them has a lot of room to succeed, while the others will continue to serve the segment.
While NAND flash and DRAM revenue growth is very modest, the MRAM product line is growing at a 66% rate due to the maturity of these technologies and is expected to reach $44 billion by the end of the 2032 forecast window. Note that the MRAM line represents combined discrete and embedded memory.
Economies of scale are key
The most important determinant of the success of any memory technology is cost, and cost can only be reduced by optimizing two factors: process technology and wafer volume. The second of these is a key reason why Intel recently announced that it would “shut down” Optane.
For discrete memory chips, this fact constitutes an almost insurmountable barrier to widespread adoption. With the help of embedded memory, this shouldn’t be that important or a problem for emerging memory technologies in the future.
Economies of scale factor embedded memory chips into the volume equation. Thus, for example, high-volume production of SoC and MCU wafers including MRAM will simultaneously reduce discrete MRAM production costs. Therefore, its market may grow faster than it would have been without this embedded element. This process feeds on itself to reduce the cost of emerging technologies faster than without this embedded element.
Finally, we expect emerging memory to grow rapidly over the next decade, in both embedded and discrete forms, to levels that are competitive with today’s mature technologies.